Parallel Adder and Parallel Subtractor

A Parallel Adder and Parallel Subtractor are combinational circuits used to perform multi-bit binary addition and subtraction. They process all bits simultaneously, making arithmetic operations faster and more efficient than serial arithmetic circuits.

• Produces the sum or difference along with the carry/borrow output.
• Forms the basic arithmetic unit used in digital logic design.

Binary Addition

Binary addition follows the same rules as decimal addition but uses only two digits: 0 and 1. These basic rules are used by parallel adders to add multi-bit binary numbers.

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 10 (0 with Carry = 1)

Example

Add 13 (1101) and 11 (1011):

1 1 0 1
+ 1 0 1 1
─────
1 1 0 0 0

Result: 11000₂ = 24₁₀

Binary Subtraction

Binary subtraction is similar to decimal subtraction, but for multi-bit subtraction we commonly use the 2's complement method. This is the technique used in many digital circuits and processors.

0 − 0 = 0

1 − 0 = 1

1 − 1 = 0

0 − 1 = 1 (Borrow = 1)

Example

Subtract 11 ( 1 0 1 1 ) from 13 ( 1 1 01 ).

• 1’s complement of 1011 → 0100
• Add 1 → 0101 (2’s complement)

1 1 0 1
+ 0 1 0 1
─────
1 0 0 1 0

Result: 0010₂ = 2₁₀ (Ignore the leftmost carry)

Parallel Adder

A Parallel Adder is formed by connecting multiple full adders to add multi-bit binary numbers. All corresponding bits are added simultaneously, while the carry generated by each Full Adder is passed to the next higher-order stage.

• Built by cascading multiple Full Adders.
• Each Full Adder adds one pair of input bits.
• The carry output of one stage becomes the carry input of the next stage.
• An n-bit Parallel Adder requires n Full Adders.

Working of Parallel Adder

1. The first Full Adder adds the least significant bits (A₁ and B₁) along with the input carry (C₁) to produce S₁ and C₂.
2. The carry C₂ is passed to the next Full Adder, which adds A₂ and B₂ to generate S₂ and C₃.
3. This process continues through all the Full Adders until the most significant bits are added.
4. The final stage produces the last sum bit along with the final carry-out (C_out).

Parallel Subtractor

A Parallel Subtractor is formed by connecting multiple Full Adders along with NOT gates to subtract multi-bit binary numbers using the 2's complement method. All bits are processed simultaneously, making subtraction much faster than performing it bit by bit.

• Built using multiple Full Adders and NOT gates.
• Subtraction is performed using the 2's complement of the subtrahend.
• Each stage processes one pair of input bits.
• An n-bit Parallel Subtractor requires n full adders.

Working of Parallel Subtractor

1. The subtrahend bits (B) are first complemented using NOT gates, and the initial carry (C₁ = 1) is applied to obtain the 2's complement.
2. The first Full Adder subtracts the least significant bits by adding A₁ and the 2's complement of B₁, producing the first difference bit and the carry.
3. The carry is passed to the next full adder, which repeats the same operation for the next pair of bits.
4. This process continues through all stages until the most significant bits are processed, producing the final difference and carry-out.